2）实验程序:
clk : 时钟信号 reset： 异步复位信号； pause： 暂停/启动信号 module text (clk,clr,pause,led1,led2,led3, led4,led5,led6,led7,led8,outclk); input clk,clr,pause; output[3:0]led1,led2,led3,led4; output [6:0] led5,led6,led7,led8; output outclk; reg [3:0]led1,led2,led3,led4; reg[3:0] hh,hl,msh,msl,sh,sl,mh,ml; reg[6:0]led5,led6,led7,led8; reg cn1,cn2,cn3,outclk; reg[15:0] B,Q1; parameter hz=10000000; always@(posedge clk) begin B<=hz/100000; if(B!=0) begin if (Q1==B/2-1) begin outclk<=~outclk;Q1<=0;end else Q1<=Q1+1;end else outclk<=0;end always @(posedge outclk or posedge clr ) begin if(clr) begin {msh,msl}<=8'h00; cn1<=0; end else if(pause) begin if (msl==9) begin msl<=0; if (msh==9) begin msh<=0; cn1<=1; end else msh<=msh+1; end else begin msl<=msl+1; cn1<=0; end end end always @( posedge cn1 or posedge clr) begin if (clr) begin {sh,sl}<=8'h00; cn2<=0; end else if(sl==9) begin sl<=0; if (sh==5) begin sh<=0; cn2<=1; end else sh<=sh+1; end else begin sl<=sl+1; cn2<=0; end end always@ (posedge cn2 or posedge clr) begin if(clr) begin {mh,ml}<=8'h00; end else if(ml==9) begin ml<=0; if (mh==5) begin mh<=0; cn3<=1; end else mh<=mh+1; end else begin ml<=ml+1; cn3<=0; end end always@ (posedge cn3 or posedge clr) begin if(clr) begin led7<='b0111111;led8<='b0111111; end else if(hh==2&&hl==4) begin hl<=0;hh<=0;end else begin case(hl) 0:begin led7<='b0111111;hl<=hl+1;end 1:begin led7<='b0000110;hl<=hl+1;end 2:begin led7<='b1011011;hl<=hl+1;end 3:begin led7<='b1001111;hl<=hl+1;end 4:begin led7<='b1100110;hl<=hl+1;end 5:begin led7<='b1101101;hl<=hl+1;end 6:begin led7<='b1111101;hl<=hl+1;end 7:begin led7<='b0000111;hl<=hl+1;end 8:begin led7<='b1111111;hl<=hl+1;end 9:begin led7<='b1101111;hh<=hh+1;hl<=0;end endcase case(hh) 0:begin led8<='b0111111;end
