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4.2程序设计及仿真
4.2.1分频器模块程序设计及仿真
module fpq(_10000HzOut,_25HzOut,_50MHzIn); input _50MHzIn; output _10000HzOut,_25HzOut; parameter width1=16,value1=2499; parameter width2=10,value2=499; reg _10000HzOut,_25HzOut; reg [width1-1:0] Count; reg [width2-1:0] Cnt;
always @(posedge _50MHzIn) //2500*2*10000Hz=50MHz if (Count==value1) //Binary Counter(0~2499) begin Count <= 15'd0; _10000HzOut <= ~_10000HzOut; end
else Count <= Count + 1'b1;
always @(posedge _50MHzIn) //100 000*2*25Hz=50MHz
if (Cnt==value2) //Binary Counter(0~99999) begin Cnt <= 15'd0; _25HzOut <= ~_25HzOut; end
